--- tulip_cb.c.orig	Sat May 20 10:45:58 2000
+++ tulip_cb.c	Fri Jul 14 22:50:58 2000
@@ -18,7 +18,7 @@
 */
 
 #define SMP_CHECK
-static const char version[] = "tulip.c:v0.91g-ppc 7/16/99 becker@cesdis.gsfc.nasa.gov (modified by danilo@cs.uni-magdeburg.de for XIRCOM CBE, fixed by Doug Ledford)\n";
+static const char version[] = "tulip.c:v0.91g-ppc 7/16/99 becker@cesdis.gsfc.nasa.gov\n (modified by danilo@cs.uni-magdeburg.de for XIRCOM CBE, fixed by Doug Ledford)\n (added by knabe@sannet.ne.jp for Corega CB-TXL 2000/07/14)\n";
 
 /* A few user-configurable values. */
 
@@ -326,6 +326,8 @@
 	0x11AD, 0xc115, 0xffff, PCI_ADDR0_IO, 256, 32, tulip_probe1 },
   { "ADMtek AN981 Comet",
 	0x1317, 0x0981, 0xffff, PCI_ADDR0_IO, 256, 32, tulip_probe1 },
+  { "corega FEther CB-TXL",
+	0x1113, 0x1216, 0xffff, PCI_ADDR0_IO, 256, 32, tulip_probe1 },
   { "Compex RL100-TX",
 	0x11F6, 0x9881, 0xffff, PCI_ADDR0_IO, 128, 32, tulip_probe1 },
   { "Intel 21145 Tulip",
@@ -378,6 +380,8 @@
 	HAS_MII | HAS_NWAY143 | HAS_8023X, t21142_timer },
   { "ADMtek Comet", 256, 0x0001abef,
 	MC_HASH_ONLY, comet_timer },
+  { "corega FEther CB-TXL", 256, 0x0001abef,
+	MC_HASH_ONLY, comet_timer },
   { "Compex 9881 PMAC", 128, 0x0001ebef,
 	HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer },
   { "Intel DS21145 Tulip", 128, 0x0801fbff,
@@ -393,8 +397,8 @@
 /* This matches the table above.  Note 21142 == 21143. */
 enum chips {
 	DC21040=0, DC21041=1, DC21140=2, DC21142=3, DC21143=3,
-	LC82C168, MX98713, MX98715, MX98725, AX88140, PNIC2, COMET, COMPEX9881,
-	I21145, X21142, X3201_3,
+	LC82C168, MX98713, MX98715, MX98725, AX88140, PNIC2, COMET, CBTXL,
+	COMPEX9881, I21145, X21142, X3201_3,
 };
 
 /* A full-duplex map for media types. */
@@ -418,7 +422,9 @@
 enum tulip_offsets {
 	CSR0=0,    CSR1=0x08, CSR2=0x10, CSR3=0x18, CSR4=0x20, CSR5=0x28,
 	CSR6=0x30, CSR7=0x38, CSR8=0x40, CSR9=0x48, CSR10=0x50, CSR11=0x58,
-	CSR12=0x60, CSR13=0x68, CSR14=0x70, CSR15=0x78 };
+	CSR12=0x60, CSR13=0x68, CSR14=0x70, CSR15=0x78, CSR16=0x80,
+	CSR17=0x84, CSR18=0x88, CSR19=0x8c, CSR20=0x90, CSR21=0x94,
+	CSR22=0x98, CSR23=0x9c, CSR24=0xa0};
 
 /* The bits in the CSR5 status registers, mostly interrupt sources. */
 enum status_bits {
@@ -794,7 +800,7 @@
 			put_unaligned(le16_to_cpu(value), ((u16*)dev->dev_addr) + i);
 			sum += value & 0xffff;
 		}
-	} else if (chip_idx == COMET) {
+	} else if (chip_idx == COMET || chip_idx == CBTXL) {
 		/* No need to read the EEPROM. */
 		put_unaligned(inl(ioaddr + 0xA4), (u32 *)dev->dev_addr);
 		put_unaligned(inl(ioaddr + 0xA8), (u16 *)(dev->dev_addr + 4));
@@ -979,6 +985,7 @@
 				((mii_status & 0x8000) == 0  && (mii_status & 0x7800) != 0)) {
 				int mii_reg0 = mdio_read(dev, phy, 0);
 				int mii_advert = mdio_read(dev, phy, 4);
+				int mii_reg19 = mdio_read(dev, phy, 19);
 				int reg4 = ((mii_status>>6) & tp->to_advertise) | 1;
 				tp->phys[phy_idx] = phy;
 				tp->advertising[phy_idx++] = reg4;
@@ -995,6 +1002,11 @@
 						   dev->name, reg4, tp->to_advertise);
 					mdio_write(dev, phy, 4, reg4);
 				}
+				if(chip_idx == COMET || chip_idx == CBTXL) {
+					/* Turn off low power mode *****albert */
+					mii_reg19 = ( mii_reg19 & 0xFFDF );
+					mdio_write(dev, phy, 19, mii_reg19);
+				}
 				/* Enable autonegotiation: some boards default to off. */
 				mdio_write(dev, phy, 0, mii_reg0 |
 						   (tp->full_duplex ? 0x1100 : 0x1000) |
@@ -1087,7 +1099,11 @@
 		outl(0x00001000, ioaddr + CSR12);
 		break;
 	case COMET:
-		/* No initialization necessary. */
+	case CBTXL:
+		if ( inl(ioaddr + CSR18) & 0x00800000 )
+		   outl(inl(ioaddr + CSR24) & 0x7FFFFFFF, ioaddr + CSR24);
+		outl(inl(ioaddr + CSR18) | 1, ioaddr + CSR18);
+
 		break;
 	}
 
@@ -1404,7 +1420,7 @@
 		return 0xffff;
 	}
 
-	if (tp->chip_id == COMET) {
+	if (tp->chip_id == COMET || tp->chip_id == CBTXL) {
 		if (phy_id == 1) {
 			if (location < 7)
 				return inl(ioaddr + 0xB4 + (location<<2));
@@ -1461,7 +1477,7 @@
 		return;
 	}
 
-	if (tp->chip_id == COMET) {
+	if (tp->chip_id == COMET || tp->chip_id == CBTXL) {
 		if (phy_id != 1)
 			return;
 		if (location < 7)
@@ -1556,7 +1572,7 @@
 			outl(addr_low,  ioaddr + CSR14);
 			outl(1, ioaddr + CSR13);
 			outl(addr_high, ioaddr + CSR14);
-		} else if (tp->chip_id == COMET) {
+		} else if (tp->chip_id == COMET || tp->chip_id == CBTXL) {
 			outl(addr_low,  ioaddr + 0xA4);
 			outl(addr_high, ioaddr + 0xA8);
 			outl(0, ioaddr + 0xAC);
@@ -1700,9 +1716,10 @@
 		outl(0xa00f0000, ioaddr + CSR15); 
 		udelay(5);
 		tp->csr6  = 0x32400000;
-	} else if (tp->chip_id == COMET) {
+	} else if (tp->chip_id == COMET || tp->chip_id == CBTXL) {
 		dev->if_port = 0;
-		tp->csr6 = 0x00040000;
+		/* baushg enable store_and_forward */
+		tp->csr6 = 0x00240000;
 	} else if (tp->chip_id == AX88140) {
 		tp->csr6 = tp->mii_cnt ? 0x00040100 : 0x00000100;
 	} else
@@ -3165,7 +3182,7 @@
 			data[0] = phy;
 		else if (tp->chip_id & HAS_NWAY143)
 			data[0] = 32;
-		else if (tp->chip_id == COMET)
+		else if (tp->chip_id == COMET || tp->chip_id == CBTXL)
 			data[0] = 1;
 		else
 			return -ENODEV;
@@ -3292,7 +3309,7 @@
 				outl(mc_filter[0], ioaddr + CSR14);
 				outl(3, ioaddr + CSR13);
 				outl(mc_filter[1], ioaddr + CSR14);
-			} else if (tp->chip_id == COMET) { /* Has a simple hash filter. */
+			} else if (tp->chip_id == COMET || tp->chip_id == CBTXL) { /* Has a simple hash filter. */
 				outl(mc_filter[0], ioaddr + 0xAC);
 				outl(mc_filter[1], ioaddr + 0xB0);
 			}
@@ -3443,7 +3460,9 @@
 	pcibios_read_config_word(bus, devfn, PCI_DEVICE_ID, &dev_id);
 	pcibios_read_config_byte(bus, devfn, PCI_INTERRUPT_LINE, &irq);
 	pcibios_read_config_word(bus, devfn, PCI_VENDOR_ID, &vendor_id);
-	if (dev_id == 0x0003 && vendor_id == 0x115d) 
+	if (dev_id == 0x1216) {
+		dev = tulip_probe1(bus, devfn, NULL, io & ~3, irq, CBTXL, 0);
+	} else if (dev_id == 0x0003 && vendor_id == 0x115d) 
 		dev = tulip_probe1(bus, devfn, NULL, io & ~3, irq, X3201_3, 0);
 	else
 		dev = tulip_probe1(bus, devfn, NULL, io & ~3, irq, DC21142, 0);